As computer systems and networked computer systems proliferate, and become integrated into more and more information processing systems which are vital to businesses and industries, there is an increasing need for faster information processing and greater interoperability among various systems. Currently, application programs are being run on a plurality of computer system architectures and operating systems across a plurality of network interconnections. Each program requires access to the system configuration of each system with which the program may communicate. To acquire this configuration information, the application program, or the operating system running the application program, must access the system configuration file for the target system. These configuration accesses are handled in differing ways for different systems.
The PCI (Peripheral Component Interconnect) Specification (PCI Local Bus Specification, Revision 2.1, Jun. 1, 1995), specifies the use of a register and a port to handle PCI configuration accesses. The register, which serves as a pointer, is called the Configuration Address Register. The port is called the Configuration Data Register. To support configuration operations to the PCI bus for software, certain specific addresses were required to be used, e.g. 32 bit I/O addresses of x'000 0CF8' and x'000 0CFC where the "CF8" address is used for configuration address information and the "CFC" address is used for the configuration data. The original "PowerPC" definition of a PCI Host Bridge (PHB) required that these addresses be at addresses x'000F 8000 and x'000F 801X in memory space, respectively. In implementing a common PHB for both of the above systems, it is necessary to merge both design points into an existing PowerPC PHB design.
Thus, there is a need for an improved information processing methodology and system in which system configuration information is made available on a common basis for access by a plurality of computer system specifications.